How-To Guide  ·  Allen-Bradley Logix 5000  ·  Process Control & Cascade Tuning  ·  Part 2 of 2

PIDE Cascade Control: Two-Loop Tuning From Scratch (Part 2)

Topic: PIDE Cascade Architecture  ·  Studio 5000 Logix Designer  ·  Reference platform: 5069-L306ER CompactLogix 5380  ·  Continues from Part 1: PIDE Loop Tuning From Scratch

1. What is Cascade Control?

A cascade pairs two single-loop controllers in series. The outer (primary) loop measures the variable you actually care about — product temperature, tank level, vessel pressure. Its job is to compute a setpoint, not a final actuator command. That setpoint feeds the inner (secondary) loop, which controls a faster intermediate variable — coolant flow, valve position, motor current — whose own actuator is the physical valve, drive, or motor.

The classic example: heating a vessel with steam.

If a disturbance perturbs the steam supply pressure (upstream pressure dip, downstream demand spike), the inner flow loop sees the deviation and corrects the valve position within seconds — long before the vessel temperature would even start to drift. A single-loop temperature-on-valve controller would have to wait for the temperature to deviate enough for its own integral term to react, which on a thermal mass can be minutes. Cascade is how you push the inner-loop disturbance rejection bandwidth ahead of the outer-loop dynamics.

In Studio 5000, the cascade is built from two ordinary PIDE blocks — no special instruction. The wiring (five signals) and the mode coordination are what make it a cascade rather than two independent loops. Source: 1756-RM006 PIDE Output Parameters.

2. When Cascade Earns Its Complexity

Cascade adds tuning effort, runtime complexity, and a second instrument (the inner-loop PV measurement). It earns that cost when all three of these are true:

1. The dominant disturbance enters on the inner-loop side — upstream pressure, supply temperature, fuel composition — not on the outer-loop process side. If the only disturbance is, say, the ambient heat loss from a tank, single-loop control of temperature will reject it just as well.
2. The inner-loop PV is measurable, fast, and has its own faster time constant than the outer process. Steam flow you can measure with a vortex meter at 100 ms; coolant valve position you can read directly from a positioner; motor current is built into every drive. If the inner variable cannot be measured cheaply, cascade is impractical.
3. The inner loop has a faster process response than the outer, so it can compensate for upsets before they affect the outer loop's process (1756-RM006, p.96; covered in section 4). If the two respond at a similar speed, the inner loop cannot finish its corrections before the outer process is affected.

Common applications where all three are true:

• Heat-exchanger temperature with steam or coolant flow as the inner loop
• Reactor temperature with jacket coolant flow as the inner loop
• Distillation column composition with reflux flow as the inner loop
• Tank level with discharge flow as the inner loop (volumetric balance)
• Compressor pressure with motor speed (VFD) as the inner loop
• Electric motor velocity with motor current/torque as the inner loop (motion control)

Cases where cascade is the wrong answer:

• Discrete machine control (start/stop, sequencing) — cascade is a continuous-control tool
• Loops with no separable inner variable — e.g. flow on a fixed-position orifice, where the "inner" measurement is the final variable
• Loops where the outer process is fast and the inner would have to be impossibly faster
• Single-loop tunings that already meet the disturbance-rejection spec — do not add cascade for its own sake

3. Common Cascade Patterns

Most industrial cascades fall into one of these patterns. Recognising the pattern up front tells you what to instrument, what to expect from tuning, and what the failure modes look like.

The time-constant ranges above are illustrative engineering ranges, not Rockwell figures; measure your own process.

The further apart the two time constants, the more dramatic the cascade benefit. Temperature-over-flow on a thermal process typically benefits more from cascade than pressure-over-speed on a fast-acting drive. Check the time constants before you commit.

4. The Time-Scale Separation Rule

Rockwell states this requirement in qualitative terms: for a cascaded pair of loops to work correctly, the secondary (inner) loop must have a faster process response than the primary (outer) loop, because the inner loop's process must be able to compensate for any upsets before these upsets affect the outer loop's process. In the steam example, if steam flow drops, the steam flow must be able to increase as a result of the inner controller's action before the liquid temperature is affected (1756-RM006, p.96; the same rule for PlantPAx PPID cascades is in PROCES-RM215, p.765).

Neither manual gives a numeric ratio between the inner and outer time constants, so this guide does not use one. Compare the two step tests instead: the inner loop, once tuned, should finish correcting a disturbance while the outer PV has barely started to move. If the outer PV visibly moves before the inner loop has settled, the separation is not there and cascade will add little.

In the rest of this guide, τ_inner-CL is the inner loop's closed-loop time constant after tuning (the λ you chose for the inner Lambda tune), and τ_outer-OL is the outer process's open-loop time constant from a step test.

This rule also dictates the inner Lambda choice. Tune the inner loop with λ_inner = inner-τ_OL (or smaller if the actuator allows) so that τ_inner-CL ≈ τ_inner-OL. Then confirm the inner loop settles well inside the outer process's response.

Worked example

Vessel temperature loop. Outer step test (in Manual, with the inner loop holding flow constant): τ_outer-OL = 6 minutes. Inner steam-flow step test: τ_inner-OL = 8 seconds.

Choose λ_inner = 8 s. After tuning, τ_inner-CL ≈ 8 s, against an outer time constant of 6 minutes. The steam-flow loop corrects a supply upset long before the vessel temperature responds, which is the condition Rockwell describes.

Counter-example: pressure-over-flow on a small surge tank, outer τ = 8 s, inner τ = 4 s. The inner loop is still settling while the outer pressure is already responding, so it cannot compensate for upsets before they reach the outer process. Tune it as a single loop instead.

5. Wiring Two PIDE Blocks in Studio 5000

The cascade in Studio 5000 is just two PIDE blocks in the same Function Block routine with five signal connections between them. There is no “cascade block” instruction.

Plus the mode request on the inner:

• Cascade/Ratio mode on the inner — set Inner.AllowCasRat = true, then request the mode with ProgCasRatReq (Program control) or OperCasRatReq (Operator control). If AllowCasRat is false (the default), both requests are ignored. Inner.CasRat = true confirms the mode; the inner then tracks SPCascade instead of SPProg/SPOper.

That's the entire mechanical wiring. The DependIndepend bit (controller-gain form) does not need to match between the two blocks — outer and inner can use different gain forms independently. Source: 1756-RM006 PIDE Output Parameters and PIDE Structure.

Engineering-units consistency

The outer's CVEU is a real-world value in the inner's PV span — for a temperature→flow cascade where flow is 0–500 GPM, the outer's CVEU must be a flow rate in the 0–500 GPM range, not a percentage. Set the outer's CVEUMax/CVEUMin to the inner's PVEUMax/PVEUMin so that the outer's full 0–100% CV span maps cleanly onto the inner's full PV span. If the spans do not match, the outer can drive the inner SP outside its limits.

6. The Initialization Handshake

The whole reason the InitPrimary → CVInitReq and SP → CVInitValue wires exist is to make cascade engagement bumpless — when the operator switches the inner from Auto to Cascade/Ratio, the outer should pick up the cascade SP exactly where it currently sits, with no jump in either CV.

The handshake works as follows. When the inner loop is not in Cascade/Ratio mode (e.g. inner is in Auto with an operator-set SP), the inner sets InitPrimary = true. That signal feeds the outer's CVInitReq, which tells the outer: “don't compute CV from the PID algorithm right now — set CVEU equal to CVInitValue.” Because Inner.SP is wired to Outer.CVInitValue, the outer's output tracks the inner's current setpoint (RM006 pp.94, 96-97).

When the operator engages cascade (requests Cascade/Ratio on the inner), InitPrimary is cleared once CVInitializing clears in Cascade/Ratio mode. The outer sees CVInitReq = false and resumes normal PID computation from a CV that already matches the inner's prior SP, so the transfer is bumpless.

Both wires are required. CVInitValue defaults to 0.0, so if Inner.SP is not wired to Outer.CVInitValue the outer's CVEU is forced to 0.0 while it initializes, and the inner SP steps to the bottom of its range when cascade engages, which is exactly the bump the handshake is meant to prevent.

If you forget these wires, cascade engagement causes a CV jump every time the operator switches to Cascade. Symptoms: the inner SP jumps to whatever the outer's CV happened to be, which makes the inner valve slam to a new position, which disturbs PV, which kicks the outer integral. Lasts for several minutes on a slow loop.

7. Anti-Windup Propagation

Anti-windup signaling is the second non-obvious cascade wire pair. Without it, here is what goes wrong:

Suppose the inner loop's CV saturates high — the steam valve is wide open and the inner SP from the outer keeps climbing because the outer wants more heating than the steam supply can deliver. The inner is doing its best, but it cannot reach its SP. The outer, meanwhile, sees the temperature still below SP, so its integral term keeps accumulating — and keeps raising the inner SP. The outer's CV winds up to absurdly high values that the inner can never deliver.

When the disturbance finally clears and the steam supply recovers, the outer's CV is hugely positive, the inner's SP is hugely positive, and the temperature now overshoots wildly — sometimes for minutes — while the outer's wound-up integral unwinds. This is “reset windup” in a cascade, and it is the failure mode that WindupHOut / WindupHIn exists to prevent.

The mechanism: when the inner's CV reaches a limit (high or low depending on ControlAction) or its SP reaches SPHLimit/SPLLimit, the inner sets WindupHOut or WindupLOut true (RM006 pp.83-84). The outer, wired to receive these on WindupHIn / WindupLIn, stops accumulating its integral term in the direction that would worsen the saturation. The outer can still decrease its CV (which reduces the inner SP, eventually unsaturating the inner), but it cannot push the inner deeper into saturation.

Wire both directions always. WindupHOut→WindupHIn handles direct-acting cascades (more outer CV => more inner SP => more PV); WindupLOut→WindupLIn handles the opposite saturation. Even if you think the loop only ever saturates one direction, the wires cost nothing and prevent embarrassing surprises during commissioning. Source: 1756-RM006 PIDE Output Parameters (WindupHOut, WindupLOut).

8. Tuning Order: Inner First, Outer Second

The tuning sequence is non-negotiable: tune the inner loop fully, in isolation, before you even open the outer loop's tuning tab. Reason: the outer process gain that you will measure depends on what the inner loop does. If the inner is poorly tuned, the outer step test will produce garbage K, τ, θ numbers, and your outer tune will be wrong.

The procedure:

1. Place the outer in Manual. Operator (or program) holds the outer CV at a fixed value — this fixes the inner SP at a constant, taking the outer out of the picture entirely.
2. Tune the inner as if it were a single-loop controller (Part 1 procedure: Manual mode, open-loop step test on the inner CV, identify K/τ/θ, apply Lambda with λ_inner = inner-τ or shorter).
3. Verify the inner loop closes cleanly on a small SP step. Tighten or relax λ_inner as needed. Confirm no oscillation.
4. Switch the inner to Cascade/Ratio mode. The inner now tracks SPCascade (which equals the outer's CVEU). The outer is still in Manual; nothing should bump because the handshake (section 6) was honored.
5. Tune the outer with the inner now closed in Cascade. Outer step test: bump outer's CV (which immediately changes inner SP, which the inner tracks fast), record outer PV until it settles. Apply Lambda with a λ_outer that is clearly slower than the inner loop's closed-loop response.
6. Switch the outer to Auto. Cascade is fully engaged. Test SP tracking on the outer SP, then test disturbance rejection on the inner side (perturb the steam supply, valve position, etc.) — you should see the inner correct within seconds while outer PV barely moves.

Outer Kp rule of thumb: the outer's controller gain usually ends up noticeably smaller than what a single-loop temperature-on-valve tune would suggest (a general guideline, not a Rockwell figure). The inner loop already provides the fast dynamics, so the outer can (and must) be more conservative. If you find yourself entering an outer K_p larger than the inner K_p, something is wrong — revisit the time-scale separation (section 4).

9. Tuning the Inner Loop

Inner-loop tuning is single-loop tuning — identical to the workflow in Part 1. The only thing different is the operating context: the outer is sitting in Manual, holding the inner SP at a fixed value while you work.

1. Set outer to Manual. Confirm Outer.Manual = true. Operator writes a constant value to Outer.CVOper — a value within the inner's normal SP range, ideally near the eventual operating point.
2. Set inner to Manual. Confirm Inner.Manual = true. Wait for the inner PV to settle.
3. Set up a Studio 5000 trend on inner CV and PV with a sample period short enough to show where the PV starts to move and the shape of the curve (Part 1 section 5).
4. Step the inner CV (e.g. 10% of CV span). Record inner PV until it reaches a new steady value.
5. Identify K, τ, θ from the response (Part 1 section 6). For an inner flow loop with θ/τ < 0.1, Lambda is the right choice; for slower thermal inner loops, Cohen-Coon may serve better.
6. Compute Lambda gains with λ_inner = inner-τ_OL (Part 1 section 8). Enter into the inner PIDE block. Enter them into PGain, IGain, and DGain. With DependIndepend = 0 (independent), IGain is in 1/min; with DependIndepend = 1 (dependent), PGain is the controller gain, IGain is the integral time in min/repeat, and DGain is the derivative time in min (RM006 pp.74-75).
7. Switch inner to Auto (still operating from SPProg/SPOper, not yet cascade). Make a small SP step on the inner. Verify the response settles within ~5× λ_inner with no oscillation. Tighten or relax K_p by 25% if needed.
8. Disturbance test: bump the inner CV manually (or perturb the upstream supply if you have a way to), put the inner back in Auto, watch the inner reject the disturbance. Should settle in ~5× λ_inner.

Once the inner loop tracks SP cleanly and rejects inner-side disturbances, you are ready to close the cascade.

10. Tuning the Outer Loop

With the inner loop tuned and operating in Cascade/Ratio mode, the outer process now sees the inner loop as a fast actuator. From the outer's perspective, the “process” is the closed-loop inner plus the outer-process dynamics in series. The outer step test measures this combined process.

1. Confirm inner is in Cascade/Ratio mode and tracking SPCascade. Confirm Inner.CasRat = true.
2. Set outer to Manual. Operator holds Outer.CVOper at the current operating point.
3. Wait for outer PV to fully settle. The inner is still actively doing its job, holding inner PV at the value Outer.CV maps to.
4. Set up a Studio 5000 trend on outer CV and PV with a sample period short enough to show the dead time and the shape of the response.
5. Bump outer CV by ~10% of its span. The inner SP will jump (because SPCascade = Outer.CVEU), the inner will track the new SP within seconds, and the outer PV will then begin its slower response. Record outer PV until it settles.
6. Identify K_cascade, τ_cascade, θ_cascade from the outer step response. The dead time will be the inner-loop closed-loop time constant plus any pure delay in the outer process — usually small. The outer time constant will be dominated by the outer-process physics (thermal mass, holdup, etc.).
7. Choose a λ_outer clearly slower than the inner loop's closed-loop response (section 4). For most thermal cascades, λ_outer = τ_cascade works.
8. Compute outer Lambda gains. Enter into the outer PIDE block.
9. Switch outer to Auto. Cascade is fully engaged.
10. Test the cascade: small SP step on outer; small disturbance on inner side (close a sample valve, change supply pressure). Both should be rejected gracefully. The inner-side disturbance test is the one cascade was built for — outer PV should barely move.

If the outer wants to oscillate, the most common cause is a too-tight λ_outer. Relax it and try again. Second most common: the inner loop is not fast enough relative to the outer (revisit section 4).

11. Mode Coordination Across the Cascade

Cascade is more than just two loops chained — the modes have to coordinate. Here is the standard behavior table, and what triggers each transition:

Two coordination rules to memorise:

1. If inner leaves Cascade/Ratio mode, the outer should track. The InitPrimary signal handles this automatically — outer's CV is forced to match inner's current SP so re-engagement is bumpless.
2. If the inner saturates, propagate via WindupHIn/LIn. The outer integral should freeze in the saturation direction, even if cascade is technically still “closed.”

Both behaviors are built-in once you have wired the five signals from section 5. No additional logic required.

12. Three-Level Cascades

You can chain three PIDE blocks the same way: a primary, secondary, and tertiary, with each level's CV becoming the next level's SP. The most common example is in process steam systems: boiler pressure → steam header pressure → fuel flow, or in motion: position → velocity → current.

Wiring extends naturally:

• Tertiary.SPCascade ← Secondary.CVEU
• Secondary.SPCascade ← Primary.CVEU
• Tertiary.InitPrimary → Secondary.CVInitReq
• Secondary.InitPrimary → Primary.CVInitReq
• Tertiary.SP → Secondary.CVInitValue
• Secondary.SP → Primary.CVInitValue
• Anti-windup signals propagate similarly through both pairs of WindupHIn/LIn wires.

The time-scale rule applies at every level: each inner loop must have a faster process response than the loop that sets its setpoint, so it can compensate for upsets before they reach the level above (1756-RM006, p.96). Few real processes have that much separation across three levels, which is why three-level cascades are uncommon.

Tuning order is the same: tune the fastest (innermost) loop first with everything above it in Manual, then close one level at a time, working outward. Diminishing returns and increased commissioning effort make three-level cascades a niche tool — reach for one only when the engineering case is unambiguous.

13. Cascade with P_PIDE Add-On

The PlantPAx P_PIDE Add-On Instruction (documented in PROCES-RM013, pp.79-91) provides the functionality of the PIDE built-in instruction with a user experience consistent with the rest of the Library of Process Objects: the P_CmdSrc command-source model, links for P_Intlk interlocks, power-up setpoint, output, and loop mode settings, and an HMI faceplate. Cascade between two P_PIDE instances follows the same pattern as raw PIDE.

Differences worth knowing:

• Mode and setpoint requests go through the P_PIDE command-source model (Operator, Program, External, Override, Maintenance, Out of Service, Hand) rather than direct writes to the PIDE request inputs. Check the P_PIDE parameter list in PROCES-RM013 (supplied as an Excel attachment to the PDF) for the exact input and output names used for cascade, the initialization handshake, and windup signals; the AOI uses its own Inp_, Out_, and Val_ naming rather than the raw PIDE names.
• Confirm in the P_PIDE parameter list that the AOI exposes the cascade setpoint, initialization (CVInitReq and CVInitValue equivalents), and windup connections you need before wiring a P_PIDE cascade.
• P_PIDE has no simulation capability. The PIDE instruction it is built on is not supported in safety applications (1756-RM006 p.66), so keep any stop or trip function in a hardwired or safety-rated circuit.

Tuning follows the same approach as raw PIDE cascade — same step-test methodology and gain entry. The wrapper adds operational features around the PIDE function block. If you can tune raw PIDE cascade, the same tuning approach applies to P_PIDE cascade.

14. Troubleshooting Cascade

15. Related Guides

• Part 1: PIDE Loop Tuning From Scratch — the prerequisite for this guide. Single-loop step test, FOPDT, Lambda / Cohen-Coon / Ziegler-Nichols rules, gain forms.
• 1756-L85E ControlLogix 5580 for PlantPAx & Batch Process
• 5069-L306ER CompactLogix 5380 First-Time Setup
• Analog Signal Types: 4-20 mA, 0-10 V, RTD, Thermocouple

References

Each publication links to its landing page in the PLC Exchange Datasheet Library, which hosts the Rockwell PDF on Cloudflare R2 (docs.plcexchange.net) for fast global access. Canonical Rockwell sources remain at literature.rockwellautomation.com.

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